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1 ltc1197/ltc1197l ltc1199/ltc1199l 10-bit, 500ksps adcs in msop with auto shutdown single 2.7v supply, 250ksps, 10-bit sampling adc supply current vs sampling frequency sampling frequency (khz) 0.01 supply current ( m a) 100 1000 10000 100 1197/99 g03 10 1 0.1 0.1 1 10 1000 v cc = 5v f clk = 7.2mhz v cc = 2.7v f clk = 3.5mhz 1 2 3 4 8 7 6 5 cs +in ?n gnd v cc clk d out v ref ltc1197l 1197/99 ta01 analog input 0v to 2.7v range 2.7v 1 m f serial data link to asic, pld, mpu, dsp or shift registers the ltc ? 1197/ltc1197l/ltc1199/ltc1199l are 10-bit a/d converters with sampling rates up to 500khz. they have 2.7v (l) and 5v versions and are offered in 8-pin msop and so packages. power dissipation is typi- cally only 2.2mw at 2.7v (25mw at 5v) during full speed operation. the automatic power down reduces supply current linearly as sample rate is reduced. these 10-bit, switched-capacitor, successive approximation adcs in- clude a sample-and-hold. the ltc1197/ltc1197l have a differential analog input with an adjustable reference pin. the ltc1199/ltc1199l offer a software-selectable 2-channel mux. the 3-wire serial i/o, msop and so-8 packages, 2.7v operation and extremely high sample rate-to-power ratio make these adcs ideal choices for compact, low power high speed systems. these circuits can be used in ratiometric applications or with external references. the high impedance analog inputs and the ability to operate with reduced spans below 1v full scale (ltc1197/ltc1197l) allow direct connec- tion to signal sources in many applications, eliminating the need for gain stages. n 8-pin msop and so packages n 10-bit resolution at 500ksps n single supply: 5v or 3v n low power at full speed: 25mw typ at 5v 2.2mw typ at 2.7v n auto shutdown reduces power linearly at lower sample rates n 10-bit upgrade to 8-bit ltc1196/ltc1198 n spi and microwire tm compatible serial i/o n low cost , ltc and lt are registered trademarks of linear technology corporation. microwire is a trademark of national semiconductor corporation. n high speed data acquisition n portable or compact instrumentation n low power or battery-operated instrumentation features descriptio u applicatio s u typical applicatio u
2 ltc1197/ltc1197l ltc1199/ltc1199l operating temperature range ltc1197c/ltc1197lc ltc1199c/ltc1199lc ........................... 0 c to 70 c ltc1197i/ltc1197li ltc1199i/ltc1199li ........................ C 45 c to 85 c lead temperature (soldering, 10 sec)................. 300 c supply voltage (v cc ) ............................................... 12v voltage analog input ..................... gnd C 0.3v to v cc + 0.3v digital input ................................ gnd C 0.3v to 12v digital output .................... gnd C 0.3v to v cc + 0.3v power dissipation .............................................. 500mw storage temperature range ................. C 65 c to 150 c (notes 1, 2) ltc1197 ltc1199 symbol parameter conditions min typ max min typ max units v cc supply voltage 4 9 4 6 v v cc = 5v operation f clk clock frequency l 0.05 7.2 0.05 7.2 mhz t cyc total cycle time 14 16 clk t smpl analog input sampling time 1.5 1.5 clk t hcs hold time cs low after last clk - 13 13 ns order part number ms8 part marking s8 part marking 1197l 1197li 1197 1197i ltc1197cs8 ltc1197is8 ltc1197lcs8 ltc1197lis8 order part number ltc1197cms8 LTC1197IMS8 ltc1197lcms8 ltc1197lims8 ltbl ltja t jmax = 150 c, q ja = 175 c/w 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so cs +in ?n gnd v cc clk d out v ref order part number ms8 part marking s8 part marking 1199l 1199li 1199 1199i ltc1199cs8 ltc1199is8 ltc1199lcs8 ltc1199lis8 order part number ltc1199cms8 ltc1199ims8 ltc1199lcms8 ltc1199lims8 ltcm ltwc t jmax = 150 c, q ja = 210 c/w 1 2 3 4 cs +in ?n gnd 8 7 6 5 v cc clk d out v ref top view ms8 package 8-lead plastic msop 1 2 3 4 cs ch0 ch1 gnd 8 7 6 5 v cc clk d out d in top view ms8 package 8-lead plastic msop t jmax = 150 c, q ja = 210 c/w t jmax = 150 c, q ja = 175 c/w 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so cs ch0 ch1 gnd v cc clk d out d in absolute axi u rati gs w ww u package/order i for atio uu w ltkv ltkw ltfl ltwb consult factory for parts specified with wider operating temperature ranges. reco e ded operati g co ditio s u u u uw w the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c.
3 ltc1197/ltc1197l ltc1199/ltc1199l ltc1197 ltc1199 symbol parameter conditions min typ max min typ max units v cc = 5v operation t sucs setup time cs before first clk - 26 26 ns (see figures 1, 2) t hdi hold time d in after clk - ltc1199 26 ns t sudi setup time d in stable before clk - ltc1199 26 ns t whclk clk high time f clk = f clk(max) 40% 40% 1/f clk t wlclk clk low time f clk = f clk(max) 40% 40% 1/f clk t whcs cs high time between data transfer cycles 32 32 ns t wlcs cs low time during data transfer 13 15 clk the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v ref = 5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. C 0.05v to v cc + 0.05v ltc1197 ltc1199 parameter conditions min typ max min typ max units offset error l 2 2 lsb linearity error (note 3) l 1 1 lsb gain error l 4 4 lsb no missing codes resolution l 10 10 bits analog input range v reference input range ltc1197, v cc 6v 0.2 v cc + 0.05v v ltc1197, v cc > 6v 0.2 6 v analog input leakage current (note 4) l 1 1 m a ltc1197l ltc1199l symbol parameter conditions min typ max min typ max units v cc supply voltage 2.7 4 2.7 4 v v cc = 2.7v operation f clk clock frequency l 0.01 3.5 0.01 3.5 mhz t cyc total cycle time 14 16 clk t smpl analog input sampling time 1.5 1.5 clk t hcs hold time cs low after last clk - 40 40 ns t sucs setup time cs before first clk - 78 78 ns (see figures 1, 2) t hdi hold time d in after clk - ltc1199l 78 ns t sudi setup time d in stable before clk - ltc1199l 78 ns t whclk clk high time f clk = f clk(max) 40% 40% 1/f clk t wlclk clk low time f clk = f clk(max) 40% 40% 1/f clk t whcs cs high time between data transfer cycles 96 96 ns t wlcs cs low time during data transfer 13 15 clk the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. reco e ded operati g co ditio s u u u uw w co verter a d ultiplexer characteristics u w u
4 ltc1197/ltc1197l ltc1199/ltc1199l the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 2.7v, v ref = 2.5v (ltc1197l), f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. C 0.05v to v cc + 0.05v dy n a m ic accuracy u w v cc = 5v, v ref = 5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. ltc1197 ltc1199 symbol parameter conditions min typ max min typ max units s/(n + d) signal-to-noise plus 100khz input signal 60 60 db distortion ratio thd total harmonic distortion 100khz input signal C 64 C 64 db first 5 harmonics peak harmonic or spurious noise 100khz input signal C 68 C 68 db imd intermodulation distortion f in1 = 97.046khz, f in2 = 102.905khz 2nd order terms C 65 C 65 db 3rd order terms C 70 C 70 db v cc = 2.7v, v ref = 2.5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. ltc1197l ltc1199l symbol parameter conditions min typ max min typ max units s/(n + d) signal-to-noise plus 50khz input signal 58 58 db distortion ratio thd total harmonic distortion 50khz input signal C 60 C 60 db first 5 harmonics peak harmonic or spurious noise 50khz input signal C 63 C 63 db imd intermodulation distortion f in1 = 48.5khz, f in2 = 51.5khz 2nd order terms C 60 C 60 db 3rd order terms C 65 C 65 db ltc1197l ltc1199l parameter conditions min typ max min typ max units offset error l 2 2 lsb linearity error (note 3) l 1 1 lsb gain error l 4 4 lsb no missing codes resolution l 10 10 bits analog input range v reference input range ltc1197l 0.2 v cc + 0.05v v analog input leakage current (note 4) l 1 1 m a co verter a d ultiplexer characteristics u w u
5 ltc1197/ltc1197l ltc1199/ltc1199l ltc1197 ltc1199 symbol parameter conditions min typ max min typ max units v ih high level input voltage v cc = 5.25v l 2.4 2.4 v v il low level input voltage v cc = 4.75v l 0.8 0.8 v i ih high level input current v in = v cc l 2.5 2.5 m a i il low level input current v in = 0v l C 2.5 C 2.5 m a v oh high level output voltage v cc = 4.75v, i o = 10 m a l 4.5 4.74 4.5 4.74 v v cc = 4.75v, i o = 360 m a l 2.4 4.72 2.4 4.72 v v ol low level output voltage v cc = 4.75v, i o = 1.6ma l 0.4 0.4 v i oz hi-z output leakage cs = high l 3 3 m a i source output source current v out = 0v C 25 C 25 ma i sink output sink current v out = v cc 45 45 ma i ref reference current (ltc1197) cs = v cc l 0.001 3 m a f smpl = f smpl(max) l 0.5 1 ma i cc supply current cs = v cc l 0.001 3 0.001 3 m a f smpl = f smpl(max) l 4.5 8 5 8.5 ma p d power dissipation f smpl = f smpl(max) 22.5 25 mw the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v ref = 5v, unless otherwise noted. digital a n d dc electrical characteristics u the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 2.7v, v ref = 2.5v, unless otherwise noted. ltc1197l ltc1199l symbol parameter conditions min typ max min typ max units v ih high level input voltage v cc = 3.6v l 1.9 1.9 v v il low level input voltage v cc = 2.7v l 0.45 0.45 v i ih high level input current v in = v cc l 2.5 2.5 m a i il low level input current v in = 0v l C 2.5 C 2.5 m a v oh high level output voltage v cc = 2.7v, i o = 10 m a l 2.3 2.60 2.3 2.60 v v cc = 2.7v, i o = 360 m a l 2.1 2.45 2.1 2.45 v v ol low level output voltage v cc = 2.7v, i o = 400 m a l 0.3 0.3 v i oz hi-z output leakage cs = high l 3 3 m a i source output source current v out = 0v C 6.5 C 6.5 ma i sink output sink current v out = v cc 11 11 ma i ref reference current (ltc1197l) cs = v cc l 0.001 3.0 m a f smpl = f smpl(max) l 0.250 0.5 ma i cc supply current cs = v cc l 0.001 3 0.001 3 m a f smpl = f smpl(max) l 0.8 2 0.8 2 ma p d power dissipation f smpl = f smpl(max) 2.2 2.2 mw
6 ltc1197/ltc1197l ltc1199/ltc1199l ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v ref = 5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. ltc1197 ltc1199 symbol parameter conditions min typ max min typ max units t conv conversion time (see figures 1, 2) l 1.4 1.4 m s f smpl(max) maximum sampling frequency l 500 450 khz t ddo delay time, clk - to d out data valid c load = 20pf 68 78 68 78 ns l 100 100 ns t dis delay time, cs - to d out hi-z l 75 150 75 150 ns t en delay time, clk to d out enabled c load = 20pf l 40 68 40 68 ns t hdo time output data remains c load = 20pf l 15 55 15 55 ns valid after clk - t r d out rise time c load = 20pf l 10 20 10 20 ns t f d out fall time c load = 20pf l 10 20 10 20 ns c in input capacitance analog input on channel 20 20 pf analog input off channel 5 5 pf digital input 5 5 pf ltc1197l ltc1199l symbol parameter conditions min typ max min typ max units t conv conversion time (see figures 1, 2) l 2.9 2.9 m s f smpl(max) maximum sampling frequency l 250 210 khz t ddo delay time, clk - to d out data valid c load = 20pf 130 180 130 180 ns l 250 250 ns t dis delay time, cs - to d out hi-z l 120 250 120 250 ns t en delay time, clk to d out enabled c load = 20pf l 100 200 100 200 ns t hdo time output data remains c load = 20pf l 30 120 30 120 ns valid after clk - t r d out rise time c load = 20pf l 15 40 15 40 ns t f d out fall time c load = 20pf l 15 40 15 40 ns c in input capacitance analog input on channel 20 20 pf analog input off channel 5 5 pf digital input 5 5 pf the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 2.7v, v ref = 2.5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 4: channel leakage current is measured after the channel selection.
7 ltc1197/ltc1197l ltc1199/ltc1199l supply current vs sampling frequency supply current vs clock rate* frequency (khz) 10 8 supply current (ma) 10 12 14 16 100 1000 10000 1197/99 g01 6 4 2 0 18 20 v cc = 9v v cc = 5v v cc = 2.7v sampling frequency (khz) 0.01 supply current ( m a) 100 1000 10000 100 1197/99 g03 10 1 0.1 0.1 1 10 1000 v cc = 5v f clk = 7.2mhz v cc = 2.7v f clk = 3.5mhz supply current vs supply voltage supply voltage (v) 1 0 supply current (ma) shutdown current (na) 8 10 12 56789 1197/99 g02 6 4 0 2 3 4 2 16 14 40 50 60 30 20 0 10 80 70 shutdown mode active mode f clk = 3.5mhz t a = 25 c code 0 1.0 inl (lsbs) 0.5 0 0.5 1.0 128 256 384 512 1197/99 g04 640 768 896 1024 v cc = v ref = 5v f clk = 7.2mhz t a = 25 c inl plot frequency (khz) 0 amplitude (db) ?0 ?0 ?0 ?0 0 1197/99 g06 ?0 ?0 ?0 ?0 ?0 ?00 50 100 150 200 250 f smpl = 500khz f in = 97.045898khz ltc1197 4096 point fft frequency (khz) 1 4 enobs 5 6 7 8 10 100 1000 1197/99 g07 3 2 1 0 9 10 v cc = 2.7v f smpl = 250khz v cc = 5v f smpl = 500khz enobs vs frequency intermodulation distortion plot *part is continuously sampling, spending only a minimum amount of time in shutdown. frequency (khz) 0 amplitude (db) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?0 0 1197/99 g09 50 100 150 200 250 f smpl = 500khz f in1 = 97.045898khz f in2 = 102.905273khz code 0 1.0 dnl (lsbs) 0.5 0 0.5 1.0 128 256 384 512 1197/99 g26 640 768 896 1024 v cc = v ref = 5v f clk = 7.2mhz t a = 25 c dnl plot thd vs frequency frequency (khz) 10 thd (db) 0 100 1000 1197/99 g08 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 t a = 25 c v cc = 2.7v f smpl = 250khz v cc = 5v f smpl = 500khz typical perfor a ce characteristics uw
8 ltc1197/ltc1197l ltc1199/ltc1199l ltc1197l change in gain error vs supply voltage ltc1197l change in offset vs supply voltage supply voltage (v) 0 change in linearity (lsbs) 0 0.6 1.0 4 1197/99 g10 0.4 0.8 0.4 0.2 0.8 0.2 0.6 1.0 1 2 3 5 v ref = 2.5v f clk = 3.5mhz ltc1197l change in linearity vs supply voltage supply voltage (v) 0 change in offset (lsbs) 0.5 0 0.5 1.0 1.5 2.0 4 1197/99 g11 ?.0 ?.5 2.0 1 2 3 5 v ref = 2.5v f clk = 3.5mhz supply voltage (v) 0 change in gain error (lsbs) 0.2 0.6 1.0 4 1197/99 g12 0.2 0.6 0 0.4 0.8 0.4 0.8 1.0 1 2 3 5 v ref = 2.5v f clk = 3.5mhz ltc1197 offset error vs reference voltage ltc1197 gain error vs reference voltage ltc1197 change in linearity vs supply voltage supply voltage (v) 0 1.0 change in linearity (lsbs) 0.8 0.4 0.2 0 1.0 0.4 2 4 59 1197/99 g13 0.6 0.6 0.8 0.2 13 6 7 8 v ref = 4v f clk = 7mhz t a = 25 c ltc1197 change in offset vs supply voltage supply voltage (v) 0 2.0 change in offset (lsbs) 1.5 2.0 1.0 0.5 0 0.5 1.0 1.5 1197/99 g14 123456789 v ref = 4v f clk = 7mhz t a = 25 c ltc1197 change in gain error vs supply voltage supply voltage (v) 0 change in gain error (lsbs) 2.0 1.0 0.5 0 1.5 2.0 2 4 59 1197/99 g15 ?.5 ?.0 0.5 13 6 7 8 v ref = 4v f clk = 7mhz t a = 25 c ltc1197 linearity error vs reference voltage reference voltage (v) 0 linearity error (lsbs) 1.0 1.5 4 1197/99 f16 0.5 0 1 2 3 5 2.0 v cc = 5v f clk = 7.2mhz t a = 25 c reference voltage (v) 0 offset error (lsbs) 1.5 2.0 2.5 4 1197/99 g17 1.0 0.5 0 1 2 3 5 v cc = 5v f clk = 7.2mhz t a = 25 c reference voltage (v) 0 gain error (lsbs) 1.0 1.5 4 1197/99 f18 0.5 0 1 2 3 5 2.0 v cc = 5v f clk = 7.2mhz t a = 25 c typical perfor a ce characteristics uw
9 ltc1197/ltc1197l ltc1199/ltc1199l linearity vs temperature temperature ( c) ?5 30 0 linearity error (lsbs) 0.2 0.5 5 45 70 1197/99 g19 0.1 0.4 0.3 20 95 120 v cc = 5v v ref = 5v f clk = 7.2mhz gain error vs temperature temperature ( c) ?5 30 1.0 1.2 1.4 gain error (lsbs) 0 5 45 70 1197/99 g21 0.2 0.4 0.6 0.8 20 95 120 v cc = 5v v ref = 5v f clk = 7.2mhz offset vs temperature temperature ( c) ?5 30 1.0 offset voltage (lsbs) 0 5 45 70 1197/99 g20 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.1 20 95 120 v cc = 5v v ref = 5v f clk = 7.2mhz *as the clk frequency is decreased from 2mhz, minimum clk frequency ( d error 0.1lsb) represents the frequency at which a 0.1lsb shift in any code translation from its 2mhz value is first detected. ? maximum clk frequency represents the clock frequency at which a 0.1lsb shift in the error at any code transition from its 3.5mhz value is first detected. acquisition time vs source resistance maximum clock frequency vs supply voltage maximum clock frequency ? vs source resistance source resistance ( w ) 100 1000 0.1 acquisition time ( m s) 1 10 100 10000 1197/99 g25 v cc = v ref = 5v t a = 25 c + input r source + v in com supply voltage (v) 0 maximum clock frequency (mhz) 6 8 10 11 8 1197/99 g26 4 2 5 7 9 3 1 0 2 4 6 19 3 5 7 10 v ref = 2.5v t a = 25 c source resistance ( w ) 100 100 maximum clock frequency (khz) 1000 10000 1000 10000 1197/99 g27 v ref = v cc = 5v t a = 25 c + input r source v in input temperature ( c) ?5 0.1 minimum clock frequency (khz) 1 10 100 1000 35 15 5 25 1197/99 g22 45 65 85 105 125 v ref = 5v v cc = 5v minimum clock frequency for 0.1lsb error* vs temperature digital input threshold vs supply voltage input channel leakage current vs temperature supply voltage (v) 0 logic threshold (v) 3 4 5 8 1197/99 g23 2 1 0 2 4 6 10 t a = 25 c temperature ( c) 0 leakage current (na) 1 10 100 100 1197/99 g24 0.1 0.01 0.001 25 50 75 125 v ref = 5v v cc = 5v on channel off channel typical perfor a ce characteristics uw
10 ltc1197/ltc1197l ltc1199/ltc1199l cs (pin 1): chip select input. a logic low on this input enables the ltc1197/ltc1197l/ltc1199/ltc1199l. power shutdown is activated when cs is brought high. + in, ch0 (pin 2): analog input. this input must be free of noise with respect to gnd. C in, ch1 (pin 3): analog input. this input must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. v ref (pin 5): ltc1197/ltc1197l reference input. the reference input defines the span of the a/d converter and must be kept free of noise with respect to gnd. d in (pin 5): ltc1199/ltc1199l digital data input. the a/d configuration word is shifted into this input. d out (pin 6): digital data output. the a/d conversion result is shifted out of this output. clk (pin 7): shift clock. this clock synchronizes the serial data transfer. v cc (pin 8): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. for ltc1199/ltc1199l, v ref is tied internally to this pin. + c smpl bias and shutdown circuit serial port v cc cs clk d out + in (ch0) in (ch1) micropower comparator capacitive dac sar v ref gnd pin names in parentheses refer to the ltc1199/ltc1199l (d in ) uu u pi fu ctio s block diagra w
11 ltc1197/ltc1197l ltc1199/ltc1199l load circuit for t ddo , t r , t f , t dis and t en voltage waveforms for d out rise and fall times, t r , t f d out 3k 20pf test point v cc t dis waveform 2, t en t dis waveform 1 1197/99 tc01 d out t r t f 1197/99 tc04 v oh v ol voltage waveforms for d out delay time, t ddo voltage waveforms for t dis clk d out v ih t ddo t hdo v oh v ol 1197/99 tc02 d out waveform 1 (see note 1) v ih t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control 1197/99 tc05 ltc1197/ltc1197l t en voltage waveforms 1197/99 tc03 cs 4 3 2 1 clk d out t en 123456 d in clk d out start t en 1197/99 tc06 cs ltc1199/ltc1199l t en voltage waveforms test circuits
12 ltc1197/ltc1197l ltc1199/ltc1199l overview the ltc1197/ltc1197l/ltc1199/ltc1199l are 10-bit switched-capacitor a/d converters. these sampling adcs typically draw 5ma of supply current when sampling up to 500khz (800 m a at 2.7v sampling up to 250khz). supply current drops linearly as the sample rate is reduced (see supply current vs sample rate in the typical perfor- mance characteristics). the adcs automatically power down when not performing a conversion, drawing only leakage current. they are packaged in 8-pin msop and so packages. the ltc1197l/ltc1199l operate on a single supply ranging from 2.7v to 4v. the ltc1197 operates on a single supply ranging from 4v to 9v while the ltc1199 operates from 4v to 6v. these adcs contain a 10-bit, switched-capacitor adc, a sample-and-hold and a serial port (see block diagram). although they share the same basic design, the ltc1197/ ltc1197l and ltc1199/ltc1199l differ in some re- spects. the ltc1197/ltc1197l have a differential input and have an external reference input pin. they can mea- sure signals floating on a dc common mode voltage and can operate with reduced spans down to 200mv. reduc- ing the span allows it to achieve 200 m v resolution. the ltc1199/ltc1199l have a 2-channel input multiplexer with the reference connected to the supply (v cc ) pin. they can convert the input voltage of either channel with re- spect to ground or the difference between the voltages of the two channels. serial interface the ltc1199/ltc1199l communicate with microproces- sors and other external circuitry via a synchronous, half duplex, 4-wire serial interface while the ltc1197/ ltc1197l use a 3-wire interface (see operating sequence in figures 1 and 2). these interfaces are compatible with both spi and microwire protocols without requiring any additional glue logic (see microprocessor inter- faces: motorola spi). data transfer the clk synchronizes the data transfer with each bit being transmitted and captured on the rising clk edge in both transmitting and receiving systems. the ltc1199/ ltc1199l first receives input data and then transmits back the a/d conversion result (half duplex). because of the half-duplex operation, d in and d out may be tied together allowing transmission over just three wires: cs, clk and data (d in /d out ). data transfer is initiated by a falling chip select (cs) signal. after cs falls the ltc1199/ltc1199l look for a start bit on the d in input. after the start bit is received, the 3-bit input word is shifted into the d in input which configures the ltc1199/ltc1199l and starts the conversion. after two null bits, the result of the conversion is output on the d out line in msb-first format. at the end of the data exchange cs should be brought high. this resets the ltc1199/ ltc1199l in preparation for the next data exchange. bringing cs high after the conversion also minimizes supply current if clk is left running. figure 1. ltc1197/ltc1197l operating sequence 1197/99 f01 clk cs t ddo t sucs b0* b1 b2 b3 b4 b5 b6 b7 b8 b9 null bits hi-z 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 d out hi-z *after completing the data transfer, if further clocks are applied with cs low, the adc will output zeros indefinitely t cyc (14 clks )* t smpl (1.5 clks) power down t conv (10.5 clks) applicatio s i for atio wu uu
13 ltc1197/ltc1197l ltc1199/ltc1199l 1197/99 f02 clk cs t ddo t sucs b0* b1 b2 b3 b4 b5 b6 b7 b8 b9 null bits hi-z 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 16 1 d out d in hi-z start dummy don? care odd/ sign sgl/ diff *after completing the data transfer, if further clocks are applied with cs low, the adc will output zeros indefinitely t en t cyc (16 clks)* t conv (10.5 clks) power down t smpl (1.5 clks) figure 2. ltc1199/ltc1199l operating sequence transfer and all leading zeros that precede this logical one will be ignored. after the start bit is received the remaining bits of the input word will be clocked in. further inputs on the d in pin are then ignored until the next cs cycle. multiplexer (mux) address the bits of the input word following the start bit assign the mux configuration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of the following table. in single-ended mode, all input channels are measured with respect to gnd. only the + inputs have sample-and-holds. signals applied at the C inputs must not change more than the required accuracy during the conversion. multiplexer channel selection mux address sgl/diff 1 1 0 0 odd/sign 0 1 0 1 channel # 0 + + 1 + + gnd 1197/99 ai02 the ltc1197/ltc1197l do not require a configuration input word and have no d in pin. a falling cs initiates data transfer as shown in the ltc1197/ltc1197l operating sequence. after cs falls, the second clk pulse enables d out . after two null bits, the a/d conversion result is output on the d out line in msb-first format. bringing cs high resets the ltc1197/ltc1197l for the next data exchange and minimizes the supply current if clk is continuously running. input data word (ltc1199/ltc1199l only) the ltc1199 4-bit data word is clocked into the d in input on the rising edge of the clock after cs goes low and the start bit has been recognized. further inputs on the d in pin are then ignored until the next cs cycle. the input word is defined as follows: sgl/ diff odd/ sign dummy start mux address 1197/99 ai01 start bit the first logical one clocked into the d in input after cs goes low is the start bit. the start bit initiates the data applicatio s i for atio wu uu
14 ltc1197/ltc1197l ltc1199/ltc1199l dummy bit the dummy bit is a placeholder that extends the acquisi- tion time of the adc. this bit can be either high or low and does not affect the conversion of the adc. operation with d in and d out tied together the ltc1199/ltc1199l can be operated with d in and d out tied together. this eliminates one of the lines required to communicate to the microprocessor (mpu). data is transmitted in both directions on a single wire. the processor pin connected to this data line should be configurable as either an input or an output. the ltc1199/ ltc1199l will take control of the data line and drive it low on the 4th falling clk edge after the start bit is received (see figure 3). therefore the processor port line must be switched to an input before this happens to avoid a conflict. in the typical applications section, there is an example of interfacing the ltc1199/ltc1199l with d in and d out tied together to the intel 8051 mpu. unipolar transfer curve the ltc1197/ltc1197l/ltc1199/ltc1199l are perma- nently configured for unipolar only. the input span and code assignment for this conversion type are shown in the following figures for a 5v reference. 1 2 3 4 cs clk data (d in /d out ) start sgl/diff odd/sign dummy b9 null bits b8 ltc1199/ltc1199l control data line and send a/d result back to mpu mpu controls data line and sends mux address to ltc1199/ltc1199l processor must release data line after 4th rising clk and before the 4th falling clk ltc1199/ltc1199l take control of data line on 4th falling clk 1197/99 f03 figure 3. ltc1199/ltc1199l operation with d in and d out tied together unipolar transfer curve 0v 1lsb v ref ?2lsb v ref ?1lsb v ref v in 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1197/99 ai03 unipolar output code output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb 1lsb 0v input voltage (v ref = 5.000v) 4.99512v 4.99023v 4.88mv 0v 1197/99 ai04 achieving micropower performance with typical operating currents of 5ma (ltc1197/ ltc1199) at 5v and 0.8ma (ltc1197l/ltc1199l) at 2.7v it is possible for these adcs to achieve true micropower performance by taking advantage of the automatic shutdown between conversions. in systems applicatio s i for atio wu uu
15 ltc1197/ltc1197l ltc1199/ltc1199l lower supply voltage for lower supply voltages, ltc offers the ltc1197l/ ltc1199l. these pin compatible devices offer specified performance to 2.7v supplies. operating on other than 5v supplies the ltc1197 operates from 4v to 9v supplies and the ltc1199 operates from 4v to 6v supplies. the ltc1197l/ ltc1199l operate from 2.7v to 4v supplies. to use these parts at other than 5v supplies a few things must be kept in mind. bypassing at higher supply voltages, bypass capacitors on v cc and v ref if applicable, need to be increased beyond what is necessary for 5v. for a 9v supply a 10 m f tantalum in parallel with a 0.1 m f ceramic is recommended. input logic levels the input logic levels of cs, clk and d in are made to meet ttl threshold levels on a 5v supply. when the supply voltage varies, the input logic levels also change. for the adc to sample and convert correctly, the digital inputs have to meet logic low and high levels relative to the operating supply voltage (see typical curve of digital input logic threshold vs supply voltage). if achieving mi- cropower consumption is desirable, the digital inputs must go rail-to-rail between v cc and ground (see achiev- ing micropower performance section). clock frequency the maximum recommended clock frequency is 7.2mhz for the ltc1197/ltc1199 running off a 5v supply and 3.5mhz for the ltc1197l/ltc1199l running off a 2.7v supply. with the supply voltage changing, the maximum clock frequency for the devices also changes (see the typical curve of maximum clock rate vs supply voltage). if the maximum clock frequency is used, care must be taken to ensure that the device converts correctly. that convert continuously, the ltc1197/ltc1197l/ ltc1199/ltc1199l will draw their normal operating power continuously. several things must be taken into account to achieve micropower operation. shutdown figures 1 and 2 show the operating sequence of the ltc1197/ltc1197l/ltc1199/ltc1199l. the converter draws power when the cs pin is low and powers itself down when that pin is high. if the cs pin is not taken all the way to ground when it is low and not taken to v cc when it is high, the input buffers of the converter will draw current. this current may be tens of microamps. it is worthwhile to bring the cs pin all the way to ground when it is low and all the way to v cc when it is high to obtain the lowest supply current. when the cs pin is high (= supply voltage), the converter is in shutdown mode and draws only leakage current. the status of the d in and clk inputs have no effect on supply current during this time. there is no need to stop d in and clk with cs = high, except the mpu may benefit. minimize cs low time in systems that have significant time between conver- sions, lowest power drain will occur with the minimum cs low time. bringing cs low, transferring data as quickly as possible, and then returning cs high will result in the lowest possible current drain. this minimizes the amount of time the device draws power. even though the device draws more power at high clock rates, the net power is less because the device is on for a shorter time. d out loading capacitive loading on the digital output can increase power consumption. a 100pf capacitor on the d out pin can add 200 m a to the supply current at a 7.2mhz clock frequency. the extra 200 m a goes into charging and dis- charging the load capacitor. the same goes for digital lines driven at a high frequency by any logic. the c ? v ? f currents must be evaluated and the troublesome ones minimized. applicatio s i for atio wu uu
16 ltc1197/ltc1197l ltc1199/ltc1199l mixed supplies it is possible to have a microprocessor running off a 5v supply and communicate with the adc operating on 3v or 9v supplies. the requirement to achieve this is that the outputs of cs, clk and d in from the mpu have to be able to trip the equivalent inputs of the adc and the output of the adc must be able to toggle the equivalent input of the mpu (see typical curve of digital input logic threshold vs supply voltage). with the ltc1197 operating on a 9v supply, the output of d out may go between 0v and 9v. the 9v output may damage the mpu running off a 5v supply. the way to solve this problem is to have a resistor divider on d out (figure 4) and connect the center point to the mpu input. it should be noted that to get full shutdown, the cs input of the adc must be driven to the v cc voltage. this would require adding a level shift circuit to the cs signal in figure 4. sample-and-hold the ltc1197/ltc1197l/ltc1199/ltc1199l provide a built-in sample-and-hold (s /h) function to acquire sig- nals. the s /h of the ltc1197/ltc1197l acquires input signals for the + input relative to the C input during the t smpl time (see figure 1). however the s /h of the ltc1199/ ltc1199l can sample input signals from the + input relative to ground and from the C input relative to ground in addition to acquiring signals from the + input relative to the C input (see figure 5) during t smpl . single-ended inputs the sample-and-hold of the ltc1199/ltc1199l allows conversion of rapidly varying signals. the input voltage is sampled during the t smpl time as shown in figure 5. the sampling interval begins as the odd/sgn bit is shifted in and continues until the falling clk edge after the dummy bit is received. on this falling edge, the s/h goes into hold mode and the conversion begins. differential inputs with differential inputs, the adc no longer converts just a single voltage but rather the difference between two volt- ages. in this case, the voltage on the selected + input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. however, the volt- age on the selected C input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the differencing operation may not be per- formed accurately. the conversion time is 10.5 clk cycles. therefore, a change in the C input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the C input this error would be: v error (max) = v peak ? 2 ? p ? f(C) ? 10.5/f clk where f(C) is the frequency of the C input voltage, v peak is its peak amplitude and f clk is the frequency of the clk. in most cases v error will not be significant. for a 60hz signal on the C input to generate a 1/4lsb error (1.22mv) with the converter running at clk = 7.2mhz, its peak value would have to be 2.22v. figure 4. interfacing a 9v-powered ltc1197 to a 5v system board layout considerations grounding and bypassing the ltc1197/ltc1197l/ltc1199/ltc1199l should be used with an analog ground plane and single point ground- ing techniques. the gnd pin should be tied directly to the ground plane. the v cc pin should be bypassed to the ground plane using a 1 m f tantalum capacitor with leads as short as possible. all analog inputs should be referenced directly to the single point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. applicatio s i for atio wu uu +in ?n gnd v cc clk d out v ref 4.7k 4.7k 6v 4.7 m f mpu (e.g. 8051) 5v p1.4 p1.3 p1.2 1197/99 f04 differential inputs common mode range 0v to 6v 9v ltc1197 9v optional level shift cs
17 ltc1197/ltc1197l ltc1199/ltc1199l clk d in d out ??input ?input sample hold ??input must settle during this time t smpl t conv cs sgl/diff start dummy odd/sgn don? care 1st bit test ?input must settle during this time 1197/99 f05 figure 5. ltc1199/ltc1199l + and C input settling windows analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1197/ ltc1197l/ltc1199/ltc1199l have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem if source resistances are less than 200 w or high speed op amps are used (e.g., the lt ? 1224, lt1191, lt1226 or lt1215). however, if large source resistances are used or if slow settling op amps drive the inputs, take care to ensure that the transients caused by the current spikes settle completely before the conversion begins. + input settling the input capacitor of the ltc1197/ltc1197l is switched onto the + input in the falling edge of cs and the sample time continues until the second falling clk edge (see figure 1). however, the input capacitor of the ltc1199/ ltc1199l is switched onto + input after odd/sgn is clocked into the adc and remains there until the fourth falling clk edge (see figure 5). the sample time is 1.5 clk cycles before conversion starts. the voltage on the + figure 6. analog equivalent circuit input must settle completely within t smpl for the adc to perform an accurate conversion. minimizing r source + and c1 will improve the input settling time (see figure 6). if a large + input source resistance must be used, the sample time can be increased by using a slower clk frequency. C input settling at the end of t smpl , the input capacitor switches to the C input and conversion starts (see figures 1 and 5). during the conversion the + input voltage is effectively held by the sample-and-hold and will not affect the applicatio s i for atio wu uu r on = 200 w c in = 20pf ltc1197/ltc1197l ltc1199/ltc1199l ? input r source + v in + c1 input r source v in c2 1197/99 f06
18 ltc1197/ltc1197l ltc1199/ltc1199l conversion result. however, it is critical that the C input voltage settles completely during the first clk cycle of the conversion time and be free of noise. minimizing r source C and c2 will improve settling time (see figure 6). if a large C input source resistance must be used, the time allowed for settling can be extended by using a slower clk frequency. input op amps when driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see figure 5). again, the + and C input sampling times can be extended as described above to accommodate slower op amps. high speed op amps such as the lt1224, lt1191, lt1226 or lt1215 can be made to settle well even with the minimum settling window of 200ns which occurs at the maximum clock rate of 7.2mhz. source resistance the analog inputs of the ltc1197/ltc1197l/ltc1199/ ltc1199l look like a 20pf capacitor (c in ) in series with a 200 w resistor (r on ) as shown in figure 6. c in gets switched between the selected + and C inputs once during each conversion cycle. large external source resis- tors and capacitors will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle within the allowed time. rc input filtering it is possible to filter the inputs with an rc network as shown in figure 7. for large values of c f (e.g., 1 m f), the capacitive input switching currents are averaged into a net dc current. therefore, a filter should be chosen with a small resistor and large capacitor to prevent dc drops across the resistor. the magnitude of the dc current is approximately i dc = 20pf(v in /t cyc ) and is roughly pro- portional to v in . when running at the minimum cycle time of 2 m s, the input current equals 50 m a at v in = 5v. in this case a filter resistor of 10 w will cause 0.1lsb of full-scale error. if a larger filter resistor must be used, errors can be eliminated by increasing the cycle time. input leakage current input leakage currents can also create errors if the source resistance gets too large. for instance, the maximum input leakage specification of 1 m a (at 85 c) flowing through a source resistance of 1k will cause a voltage drop of 1mv or 0.2lsb. this error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve of input channel leakage current vs temperature). reference inputs the voltage on the reference input of the ltc1197/ ltc1197l defines the voltage span of the a/d converter. the reference input transient capacitive switching cur- rents are due to the switched-capacitor conversion tech- nique used in these adcs (see figure 8). during each bit test of the conversion (every clk cycle), a capacitive current spike will be generated on the reference pin by the adc. these current spikes settle quickly and do not cause a problem. reduced reference operation the minimum reference voltage of the ltc1199 is 4v and the minimum reference voltage of the ltc1199l is 2.7v because the v cc supply and reference are internally tied together. however, the ltc1197/ltc1197l can operate with reference voltages below 1v. figure 7. rc input filtering figure 8. reference input equivalent circuit applicatio s i for atio wu uu r filter v in c f 1197/99 f07 ltc1199 + i dc r on 5pf to 25pf ltc1197 ref r out v ref every clk cycle 5 4 gnd 1197/99 f08
19 ltc1197/ltc1197l ltc1199/ltc1199l the effective resolution of the ltc1197/ltc1197l can be increased by reducing the input span of the converter. the ltc1197/ltc1197l exhibits good linearity and gain over a wide range of reference voltages (see typical curves of linearity and full-scale error vs reference voltage). how- ever, care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the con- verter. the following factors must be considered when operating at low v ref values. 1. offset 2. noise 3. conversion speed (clk frequency) offset with reduced v ref the offset of the ltc1197/ltc1197l has a larger effect on the output code when the adc is operated with reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of ltc1197 offset error vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 1mv which is 0.2lsb with a 5v reference becomes 1lsb with a 1v reference and 5lsbs with a 0.2v reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the C input of the ltc1197/ltc1197l. noise with reduced v ref the total input referred noise of the ltc1197/ltc1197l can be reduced to approximately 200 m v peak-to-peak using a ground plane, good bypassing, good layout tech- niques and minimizing noise on the reference inputs. this noise is insignificant with a 5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. for operation with a 5v reference, the 200 m v noise is only 0.04lsb peak-to-peak. in this case, the ltc1197/ ltc1197l noise will contribute virtually no uncertainty to the output code. however, for reduced references, the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1v reference, this same 200 m v noise is 0.2lsb peak-to-peak. this will reduce the range of input volt- ages over which a stable output code can be achieved. if the reference is further reduced to 200mv, the 200 m v of noise becomes equal to 1lsb and a stable code may be difficult to achieve. in this case, averaging readings may be necessary. this noise data was taken in a very clean setup. any setup- induced noise (noise or ripple on v cc , v ref or v in ) will add to the internal noise. the lower the reference voltage to be used, the more critical it becomes to have a clean, noise- free setup. conversion speed with reduced v ref with reduced reference voltages the lsb step size is reduced and the ltc1197/ltc1197l internal comparator overdrive is reduced. therefore, it may be necessary to reduce the maximum clk frequency when low values of v ref are used. input divider it is ok to use an input divider on the reference input of the ltc1197/ltc1197l as long as the reference input can be made to settle within the bit time at which the clock is running. when using a larger value resistor divider on the reference input, the C input should be matched with an equivalent resistance. bypassing reference input with divider bypassing the reference input with a divider is also pos- sible. however, care must be taken to make sure that the dc voltage on the reference input will not drop too much below the intended reference voltage. applicatio s i for atio wu uu
20 ltc1197/ltc1197l ltc1199/ltc1199l signal-to-noise ratio t he signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. this includes distortion as well as noise products and for this reason it is sometimes referred to as signal-to-noise + distortion [s/(n + d)]. the output is band limited to frequencies from dc to one half the sampling frequency. figure 9 shows spectral content from dc to 250khz which is 1/2 the 500khz sampling rate. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: enob = [s/(n + d) C1.76]/6.02 where s/(n + d) is expressed in db. at the maximum sampling rate of 500khz, the ltc1197 maintains 9.5 enobs or better to 200khz. above 200khz, the enobs gradually decline, as shown in figure 10, due to increasing second harmonic distortion. the noise floor remains approximately 100db. frequency (khz) 0 amplitude (db) ?0 ?0 ?0 ?0 0 1197/99 g06 ?0 ?0 ?0 ?0 ?0 ?00 50 100 150 200 250 f smpl = 500khz f in = 97.045898khz figure 9. this clean fft of a 97khz input shows remarkable performance for an adc sampling at the 500khz rate frequency (khz) 1 4 enobs 5 6 7 8 10 100 1000 1197/99 g07 3 2 1 0 9 10 v cc = 2.7v f smpl = 250khz v cc = 5v f smpl = 500khz figure 10. dynamic accuracy is maintained up to an input frequency of 200khz for the ltc1197 and 50khz for the ltc1197l applicatio s i for atio wu uu
21 ltc1197/ltc1197l ltc1199/ltc1199l microprocessor interfaces the ltc1197/ltc1197l/ltc1199/ltc1199l can inter- face directly (without external hardware to most popular microprocessor (mpu) synchronous serial formats (see table 1). if an mpu without a dedicated serial port is used, then three or four of the mpus parallel port lines can be programmed to form the serial link. included here is one serial interface example and one example showing a parallel port programmed to form the serial interface. motorola spi (mc68hc05c4, mc68hc11) the mc68hc05c4 has been chosen as an example of an mpu with a dedicated serial port. this mpu transfers data msb-first and in 8-bit increments. with two 8-bit trans- fers, the a/d result is read into the mpu. the first 8-bit transfer sends the d in word to the ltc1199 and clocks the two adc msbs (b9 and b8) into the mpu. the second 8- bit transfer clocks the next 8 bits, b7 through b0, of the adc into the mpu. anding the first mpu received byte with 03hex clears the six msbs. notice how the position of the start bit in the d in word is used to position the a/d result so that it is right- justified in two memory locations. table 1. microprocessor with hardware serial interfaces compatible with the ltc1197/ltc1197l/ltc1199/ltc1199l part number type of interface motorola mc6805s2,s3 spi mc68hc11 spi mc68hc05 spi rca cdp68hc05 spi hitachi hd6301 sci synchronous hd6303 sci synchronous hd6305 sci synchronous hd63701 sci synchronous hd63705 sci synchronous hd64180 csi/o national semiconductor cop400 family microwire tm cop800 family microwire/plus tm nsc8050u microwire/plus hpc16000 family microwire/plus texas instruments tms7000 family serial port tms320 family serial port microchip technology pic16c60 family spi, sci synchronous pic16c70 family spi, sci synchronous microwire and microwire/plus are trademarks of national semiconductor corp. typical applicatio s u
22 ltc1197/ltc1197l ltc1199/ltc1199l data exchange between ltc1199 and mc68hc05c4 hardware and software interface to motorola mc68hc05c4 label mnemonic comments start bclrn bit 0 port c goes low (cs goes low) lda load ltc1199 d in word into acc sta load ltc1199 d in word into spi from acc transfer begins tst test status of spif bpl loop to previous instruction if not done with transfer lda load contents of spi data register into acc (d out msbs) sta start next spi cycle and clear 6 msbs of the first d out word sta store in memory location a (msbs) tst test status of spif bpl loop to previous instruction if not done with transfer bsetn set b0 of port c (cs goes high) lda load contents of spi data register into acc. (d out lsbs) sta store in memory location a + 1 (lsbs) mpu transmit word cs clk d out mpu received word d in 1 odd/ sign x x x x sgl/ diff xxxxxxxx start bit byte 1 byte 2 (dummy) x = don? care start dummy sgl/ diff don? care b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 odd/ sign dummy ?? ?? 00b9b8 b7 b6 b5 b4 b3 b2 b1 b0 2nd transfer 1st transfer 1197/99 ta03 d out from ltc1199 stored in mc68hc05c4 location a + 1 lsb msb location a byte 2 byte 1 1197/99 ta05 b7 b6 b5 b4 b3 b2 b1 b0 00 00 00b9b8 typical applicatio s u 1197/99 ta04 clk d in cs analog inputs c0 sck d out miso mosi mc68hc05c4 ltc1199
23 ltc1197/ltc1197l ltc1199/ltc1199l interfacing to the parallel port of the intel 8051 family the intel 8051 has been chosen to demonstrate the interface between the ltc1199 and parallel port micro- processors. normally, the cs, clk and d in signals would be generated on three port lines and the d out signal read on a fourth port line. this works very well. however, we will demonstrate here an interface with the d in and d out of the ltc1199 tied together as described in the serial interface section. this saves one wire. the 8051 first sends the start bit and mux address to the ltc1199 over the data line connected to p1.2. then p1.2 is reconfigured as an input (by writing to it a one) and the 8051 reads back the 8-bit a/d result over the same data line. label mnemonic operand comments mov a, #ffh d in word for ltc1199 setb p1.4 make sure cs is high clr p1.4 cs goes low mov r4, #04 load counter loop 1 rlc a rotate d in bit into carry clr p1.3 clk goes low mov p1.2, c output d in bit into carry setb p1.3 clk goes high djnz r4, loop 1 next bit mov p1, #04 bit 2 becomes an input clr p1.3 clk goes low mov r4, #0ah load counter loop mov c, p1.2 read data bit into carry rlc a rotate data bit into acc setb p1.3 clk goes high clr p1.3 clk goes low djnz r4, loop next bit mov r2, a store msbs in r2 mov c, p1.2 read data bit into carry setb p1.3 clk goes high clr p1.3 clk goes low clr a clear acc rlc a rotate data bit from carry to acc mov c, p1.2 read data bit into carry rrc a rotate right into acc rrc a rotate right into acc mov r3, a store lsbs in r3 setb p1.4 cs goes high d out from ltc1199 stored in 8051 ram 1 cs clk data (d in /d out ) start odd/ sign dummy b9 ltc1199 sends a/d result back to 8051 p1.2 8051 p1.2 outputs data to ltc1199 8051 p1.2 reconfigured as an input after the 4th rising clk and before the 4th falling clk ltc1199 takes control of data line on 4th falling clk 234 sgl/ diff b8 b7 b6 b5 b4 b3 b2 b1 b0 1197/99 ta08 r2 1197/99 ta07 msb b9 b8 b7 b6 b5 b4 b3 b2 r3 lsb b1 b0 0 0 0 0 0 0 typical applicatio s u cs clk d out d in ltc1199 analog inputs p1.4 p1.3 p1.2 8051 mux address a/d result 1197/99 ta06
24 ltc1197/ltc1197l ltc1199/ltc1199l a quick look circuit for the ltc1197 users can get a quick look at the function and timing of the ltc1197 by using the following simple circuit (figure 11). v ref is tied to v cc . v in is applied to the +in input and the C in input is tied to the ground. cs is driven at 1/16 the clock rate by the 74hc161 and d out outputs the data. the output data from the d out pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of cs (figure 12). note that after the lsb is clocked out, the ltc1197 clocks out zeros until cs goes high. also note that with the resistor divider on d out the output goes midway between v cc and ground when in the high impedance mode. figure 11. quick look circuit for the ltc1197 clk cs d out fill zeroes high impedance 2 null bits msb (b9) lsb (b0) vertical: 5v/div horizontal: 10 m s/div figure 12. scope photo of the ltc1197 quick look circuit waveforms showing a/d output 1001001001 (249 hex ) typical applicatio s u clr clk a b c d p gnd v cc rc qa qb qc qd t load 74hc161 v in to oscilloscope d out clk cs 1197/99 f11 v cc clk d out v ref ltc1197 cs +in ?n gnd 1 m f 5v 10k clk in 7.2mhz max 10k 5v +
25 ltc1197/ltc1197l ltc1199/ltc1199l figure 13. the ltc1199 digitizes resistive touchscreen x and y axis voltages. the adcs auto shutdown feature helps maximize battery life in portable touchscreen equipment resistive touchscreen interface figure 13 shows the ltc1199 in a 4-wire resistive touch- screen application. transistor pairs q1-q3, q2-q4 apply 5v and ground to the x axis and y axis, respectively. the ltc1199, with its 2-channel multiplexer, digitizes the voltage generated by each axis and transmits the conver- sion results to the systems processor through a serial interface. rc combinations r1c1, r2c2 and r3c3 form lowpass filters that attenuate noise from possible sources such as the processor clock, switching power supplies and bus signals. the 74hc14 inverter is used to detect screen contact both during a conversion sequence and to trigger its start. using the single channel ltc1197, 5-wire resistive touchscreens are as easily accommodated. typical applicatio s u c4 1000pf c6 1000pf c5 1000pf r8 4.7k r11 100k r12 100k r6 4.7k r3 10 w r7 100k r1 100 w ltc1199 r2 100 w r7 100k r9 100k q1 2n2907 q3 2n2222a q2 2n2907 r10 4.7k 74hc14 r6 4.7k 5v y + x y x + touch sense chip select serial clk data in data out q4 2n2222a c7 1000pf c2 1 m f c1 1 m f 1197/99 f13 c3 10 m f 1 2 3 4 8 7 6 5 v cc clk d out d in cs ch0 ch1 gnd +
26 ltc1197/ltc1197l ltc1199/ltc1199l battery current monitor the ltc1197l/ltc1199l are ideal for 3v systems. fig- ure 14 shows a 2.7v to 4v battery current monitor that draws only 45 m a at 3v from the battery it monitors, sampling at a 1hz rate. to minimize supply current, the microprocessor uses the ltc1152 shdn pin to turn on the op amp prior to making a measurement and then turn it off after the measurement has been made. the battery current is sensed with the 0.005 w resistor and amplified by the ltc1152. the ltc1197l digitizes the amplifier output and sends it to the microprocessor in serial format. after each sample the ltc1197l automatically powers down. the lt1004 provides the full-scale refer- ence for the adc. the circuits 45 m a supply current is dominated by the reference and the op amp. the circuit can be located near the battery and data transmitted serially to the microprocessor. figure 14. this 0a to 2a battery current monitor draws only 45 m a from a 3v battery typical applicatio s u + ltc1152 shdn 240k 56k to m p 100 w 2k 0.005 w 2a full scale 500pf 2.7v to 4v 1 m f 1 m f 0.1 m f lt1004-1.2 1 2 3 4 8 7 6 5 cs +in ?n gnd v cc clk d out v ref ltc1197l l o a d +
27 ltc1197/ltc1197l ltc1199/ltc1199l dimensions in inches (millimeters), unless otherwise noted. s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) ms8 package 8-lead plastic msop (ltc dwg # 05-08-1660) msop (ms8) 1100 * dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.006" (0.152mm) per side 0.021 0.006 (0.53 0.015) 0 ?6 typ seating plane 0.007 (0.18) 0.043 (1.10) max 0.009 ?0.015 (0.22 ?0.38) 0.005 0.002 (0.13 0.05) 0.034 (0.86) ref 0.0256 (0.65) bsc 12 3 4 0.193 0.006 (4.90 0.15) 8 7 6 5 0.118 0.004* (3.00 0.102) 0.118 0.004** (3.00 0.102) 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio
28 ltc1197/ltc1197l ltc1199/ltc1199l ? linear technology corporation 1997 11979fa lt/lcg 0301 2k rev a ? printed in usa related parts part number sample rate power dissipation description 8-bit, pin compatible serial output adcs ltc1096/ltc1096l 33khz/15khz 0.5mw* 1-channel, unipolar operation with reference input, 5v/3v ltc1098/ltc1098l 33khz/15khz 0.6mw* 2-channel, unipolar operation, 5v/3v ltc1196 1mhz/383khz 20mw 1-channel, unipolar operation with reference input, 5v/3v ltc1198 750khz/287khz 20mw* 2-channel, unipolar operation, 5v/3v 10-bit serial i/o adcs ltc1090 25khz 5mw 8-channel, bipolar or unipolar operation, 5v ltc1091 30khz 7.5mw 2-channel, unipolar operation, 5v ltc1092 35khz 5mw 2-channel, unipolar operation with reference input, 5v ltc1093 25khz 5mw 6-channel, bipolar or unipolar operation, 5v ltc1094 25khz 5mw 8-channel, bipolar or unipolar operation, 5v ltc1283 15khz 0.5mw 8-channel, bipolar or unipolar operation, 3v 12-bit serial i/o adcs ltc1285/ltc1288 7.5khz/6.6khz 0.4mw/0.6mw* 1-channel with reference (ltc1285), 2-channel (ltc1288), 3v ltc1286/ltc1298 12.5khz/11.1khz 1.3mw/1.7mw* 1-channel with reference (ltc1286), 2-channel (ltc1298), 5v ltc1287 30khz 3mw 1-channel, unipolar operation, 3v ltc1289 33khz 3mw 8-channel, bipolar or unipolar operation, 3v ltc1290 50khz 30mw 8-channel, bipolar or unipolar operation, 5v ltc1291 54khz 30mw 2-channel, unipolar operation, 5v ltc1292 60khz 30mw 1-channel, unipolar operation, 5v ltc1293 46khz 30mw 6-channel, bipolar or unipolar operation, 5v ltc1294 46khz 30mw 8-channel, bipolar or unipolar operation, 5v ltc1296 46khz 30mw 8-channel, bipolar or unipolar operation, 5v ltc1297 50khz 30mw 1-channel, unipolar operation, 5v ltc1400 400khz 75mw** 1-channel, bipolar or unipolar operation, internal reference, 5v ltc1594/ltc1594l 20khz/12.5khz 1.6mw/0.5mw* 4-channel, unipolar operation, 5v/3v ltc1598/ltc1598l 20khz/12.5khz 1.6mw/0.5mw* 8-channel, unipolar operation, 5v/3v part number description comments low power references lt1004 micropower voltage reference 0.3% max, 20ppm/ c typ, 10 m a max lt1019 precision bandgap reference 0.05% max, 5ppm/ c max lt1236 precision low noise reference 0.05% max, 5ppm/ c max, so package lt1460-2.5 micropower precision series reference 0.075% max, 10ppm/ c max, 130 m a max, so package lt1634 micropower precision reference 0.05% max, 25ppm/ c max, 7 m a max, msop package *these devices have auto shutdown which reduces power dissipation linearly as sample rate is reduced from f smpl(max) . **has nap and sleep shutdown modes. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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